一、input_array约束为axisvoid array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {#pragma HLS INTERFACE axis register both portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}rtl仿真结果注意数组指定axis的时候不需要指定depth因为数组默认就已经给定了depth了数组的大小就是depth如果是指针变量就不行指针变量约束为axis,是需要开发者显示的指定detph,否则是死锁的。二、input_array约束为s_axilitevoid array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {#pragma HLS INTERFACE s_axilite register portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}需要注意的是约束为axilte并不是将其约束为寄存器了上述代码将其约束为axilite_ram了。修改代码后void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {#pragma HLS INTERFACE s_axilite register depth4 portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}综合还是生成axilite_bram了。再次修改void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {#pragma HLS ARRAY_PARTITION variabled_i complete dim1#pragma HLS INTERFACE s_axilite register depth4 portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}三、input_array约束为m_axi------------非常常用void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {#pragma HLS INTERFACE m_axi portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}上述是数组设计约束为m_axi的时候不需要指定depth。如果是指针需要指定depth.四、input_array约束为ap_hsvoid array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {//#pragma HLS INTERFACE m_axi depth0 portd_i#pragma HLS INTERFACE ap_hs portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}五、input_array约束为ap_memory---------非常常用void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {//#pragma HLS INTERFACE m_axi depth0 portd_i#pragma HLS INTERFACE ap_memory portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}六、input_array约束为bram---------非常常用void array_FIFO (dout_t d_o[4], din_t d_i[4], didx_t idx[4]) {//#pragma HLS INTERFACE m_axi depth0 portd_i#pragma HLS INTERFACE bram portd_iint i;// Breaks FIFO interface d_o[3] d_i[2];For_Loop: for (i0;i4;i) {d_o[i] d_i[idx[i]];//d_o[i] d_i[i];}}七、input_array约束为ap_fifo八、input_array约束为ap_bus几乎很少用到用到再说九、axilite ap_memory接口的bram-------非常常用这个只要你将数组约束为axilite默认就是生成ap_memorylite接口的bram资源注意这里是生成ram了不只是接口。这个是生成了实实在在的存储资源而不是存储资源接口。
