相关阅读静态时序分析https://blog.csdn.net/weixin_45791458/category_12567571.html?spm1001.2014.3001.5482当设计中出现锁存器时静态时序分析就会变得更加复杂。一种称为时间借用(Time Borrowing)或者周期窃取(Cycle Stealing)的技术使得基于锁存器的设计相比基于触发器的设计具有明显优势因为电平敏感的锁存器在一个有效时钟脉冲的持续时间内是透明的这种技术可以放宽设计中常见的沿到沿时序要求。本文将介绍面向锁存器的传统时序分析方法PrimeTime在2014版本后推出了新一代分析方法这不在本文的讨论范围之内。时序借用的概念对于锁存器而言时钟的一个沿会使锁存器进入透明状态也就是说它会打开锁存器使锁存器的输出与输入数据保持一致这个时钟沿称为开启沿(Opening edge)。时钟的另一个沿会关闭锁存器也就是说输入数据的任何变化将不再反映到锁存器输出端这个时钟沿称为关闭沿(Closing edge)。对于触发器而言输入数据应当在时钟有效沿到来之前就已经在锁存器输入端就绪。然而由于锁存器在时钟为有效电平时处于透明状态输入数据可以在时钟有效沿之后到达也就是说它可以从下一个周期借用时间。如果发生了时间借用那么下一个周期从该锁存器到下一个时序单元的可用时间就会减少。图1展示了一个使用上升沿进行时间借用的例子。如果输入数据DIN在时刻A先于10ns时CLK的上升沿就已经准备好那么随着锁存器在该上升沿打开输入数据会直接流向锁存器的输出。如果输入数据如图中延迟的DIN那样在时刻B才到达则会借用时间Tb。然而这会减少从该锁存器到下一个触发器UFF2的可用时间即原本可以使用整个时钟周期的时间现在只剩下时间Ta。图1 时序借用总得来说锁存器的有以下三种行为1、如果输入数据在锁存器开启沿之前到达那么其行为模型与触发器完全一致开启沿捕获数据而锁存器的时钟引脚会作为下一条时序路径的起点将数据发射出去。2、如果输入数据在锁存器透明状态时到达即在开启沿与关闭沿之间下一条时序路径的起点不再是锁存器的时钟引脚而是锁存器的数据引脚借用的时间则会影响下一条时序路径。3、如果输入数据在锁存器关闭沿之后到达则属于时序违例。图2展示了图1所示设计中正裕量、零裕量以及负裕量即发生违例情况下的输入数据到达时间区域。图2 锁存器时序违例窗口图3(a)展示了两个触发器夹一个锁存器的情况注意其中锁存器ULAT1是由反相时钟触发。图3(b)则给出了时间借用场景下的波形。时钟周期为10ns数据由UFF0在0ns发射但数据路径耗时7ns锁存器ULAT1在5ns时打开因此从ULAT1到UFF1的路径中借用了2nsULAT1到UFF1这条路径可用的时间只剩下3ns(5ns - 2ns)。图3 时序借用的例子1图4则展示了两个锁存器夹一个锁存器的情况以及时间借用场景下的波形注意其中锁存器U2是由反相时钟触发。时钟周期为10ns数据由U1在0ns发射但数据路径耗时8.92ns锁存器U2在5ns时打开因此从U2到U3的路径中借用了3.92nsU2到U3这条路径可用的时间只剩下1.08ns(5ns - 3.92ns)。图4 时序借用的例子2图5展示了图4所示设计中正裕量、零裕量以及负裕量即发生违例情况下的输入数据到达时间区域。图5 锁存器时序违例窗口锁存器的时序报告下面将以图3为例展示上述三种情况下的时序报告。没有时序借用的情况**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 06:52:15 2025 **************************************** Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLK) Endpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 UFF0/CK (DFFQXL) 0.00 0.00 r UFF0/Q (DFFQXL) 0.07 0.07 f U3/Y (AND2X1) 0.04 0.12 f ULAT1/D (TLATX1) 0.00 0.12 f data arrival time 0.12 clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 ULAT1/G (TLATX1) 0.00 5.00 r time borrowed from endpoint 0.00 5.00 data required time 5.00 ----------------------------------------------------------- data required time 5.00 data arrival time -0.12 ----------------------------------------------------------- slack (MET) 4.88 Time Borrowing Information ----------------------------------------------- CLK nominal pulse width 5.00 library setup time -0.03 ----------------------------------------------- max time borrow 4.97 actual time borrow 0.00 -----------------------------------------------**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 06:56:01 2025 **************************************** Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 ULAT1/G (TLATX1) 0.00 5.00 r ULAT1/Q (TLATX1) 0.05 5.05 f U2/Y (AND2X1) 0.04 5.09 f UFF1/D (DFFQXL) 0.00 5.09 f data arrival time 5.09 clock CLK (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 UFF1/CK (DFFQXL) 0.00 10.00 r library setup time -0.03 9.97 data required time 9.97 ----------------------------------------------------------- data required time 9.97 data arrival time -5.09 ----------------------------------------------------------- slack (MET) 4.88有时序借用的情况**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 07:11:25 2025 **************************************** * Some/all delay information is back-annotated. Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLK) Endpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 UFF0/CK (DFFQXL) 0.00 0.00 r UFF0/Q (DFFQXL) 6.19 6.19 f U3/Y (AND2X1) 1.48 7.67 f ULAT1/D (TLATX1) 0.00 7.67 f data arrival time 7.67 clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 ULAT1/G (TLATX1) 0.00 5.00 r time borrowed from endpoint 2.67 7.67 data required time 7.67 ----------------------------------------------------------- data required time 7.67 data arrival time -7.67 ----------------------------------------------------------- slack (MET) 0.00 Time Borrowing Information ----------------------------------------------- CLK nominal pulse width 5.00 library setup time -0.08 ----------------------------------------------- max time borrow 4.92 actual time borrow 2.67 -----------------------------------------------**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 07:13:33 2025 **************************************** * Some/all delay information is back-annotated. Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 time given to startpoint 2.67 7.67 ULAT1/D (TLATX1) 0.00 7.67 f ULAT1/Q (TLATX1) 0.09 7.76 f U2/Y (AND2X1) 0.04 7.80 f UFF1/D (DFFQXL) 0.00 7.80 f data arrival time 7.80 clock CLK (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 UFF1/CK (DFFQXL) 0.00 10.00 r library setup time -0.03 9.97 data required time 9.97 ----------------------------------------------------------- data required time 9.97 data arrival time -7.80 ----------------------------------------------------------- slack (MET) 2.17从第一个时序报告以锁存器为终点的时序路径中可以看出time borrowed from endpoint一行列出了借用的时间同时在第二个时序报告以锁存器为起点的时序路径中的time given to startpoint一行出现它们并不总是相等后面会解释原因需要注意的是发生时序借用时需要考虑两个时序路径的转换方向该例中都为下降沿。在使用report_timing命令时添加-trace_latch_borrow选项可以报告整个时序借用情况包括上一条被借用的时序路径如下所示。**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group -trace_latch_borrow Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 07:43:40 2025 **************************************** * Some/all delay information is back-annotated. Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Time is borrowed from the startpoint of this path. The following is a forward trace from the origin of the borrow. Path Segment: #1 Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLK) Endpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 UFF0/CK (DFFQXL) 0.00 0.00 r UFF0/Q (DFFQXL) 6.19 6.19 f U3/Y (AND2X1) 1.48 7.67 f ULAT1/D (TLATX1) 0.00 7.67 f data arrival time 7.67 clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 ULAT1/G (TLATX1) 0.00 5.00 r time borrowed from endpoint 2.67 7.67 data required time 7.67 ----------------------------------------------------------- data required time 7.67 data arrival time -7.67 ----------------------------------------------------------- slack (MET) 0.00 Time Borrowing Information ----------------------------------------------- CLK nominal pulse width 5.00 library setup time -0.08 ----------------------------------------------- max time borrow 4.92 actual time borrow 2.67 ----------------------------------------------- Path Segment: #2 Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 time given to startpoint 2.67 7.67 ULAT1/D (TLATX1) 0.00 7.67 f ULAT1/Q (TLATX1) 0.09 7.76 f U2/Y (AND2X1) 0.04 7.80 f UFF1/D (DFFQXL) 0.00 7.80 f data arrival time 7.80 clock CLK (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 UFF1/CK (DFFQXL) 0.00 10.00 r library setup time -0.03 9.97 data required time 9.97 ----------------------------------------------------------- data required time 9.97 data arrival time -7.80 ----------------------------------------------------------- slack (MET) 2.17 有时序违例的情况**************************************** Report : timing -path full -delay max -max_paths 1 -sort_by group -trace_latch_borrow Design : top Version: U-2022.12-SP1 Date : Sun Nov 16 07:48:30 2025 **************************************** * Some/all delay information is back-annotated. Operating Conditions: fast Library: fast Wire Load Model Mode: top Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Time is borrowed from the startpoint of this path. The following is a forward trace from the origin of the borrow. Path Segment: #1 Startpoint: UFF0 (rising edge-triggered flip-flop clocked by CLK) Endpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 UFF0/CK (DFFQXL) 0.00 0.00 r UFF0/Q (DFFQXL) 15.35 15.35 f U3/Y (AND2X1) 3.62 18.97 f ULAT1/D (TLATX1) 0.00 18.97 f data arrival time 18.97 clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 ULAT1/G (TLATX1) 0.00 5.00 r time borrowed from endpoint 4.85 9.85 data required time 9.85 ----------------------------------------------------------- data required time 9.85 data arrival time -18.97 ----------------------------------------------------------- slack (VIOLATED) -9.13 Time Borrowing Information ----------------------------------------------- CLK nominal pulse width 5.00 library setup time -0.15 ----------------------------------------------- max time borrow 4.85 actual time borrow 4.85 ----------------------------------------------- Path Segment: #2 Startpoint: ULAT1 (positive level-sensitive latch clocked by CLK) Endpoint: UFF1 (rising edge-triggered flip-flop clocked by CLK) Path Group: CLK Path Type: max Point Incr Path ----------------------------------------------------------- clock CLK (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 time given to startpoint 4.85 9.85 ULAT1/D (TLATX1) 0.00 9.85 f ULAT1/Q (TLATX1) 0.16 10.00 f U2/Y (AND2X1) 0.04 10.04 f UFF1/D (DFFQXL) 0.00 10.04 f data arrival time 10.04 clock CLK (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 UFF1/CK (DFFQXL) 0.00 10.00 r library setup time -0.03 9.97 data required time 9.97 ----------------------------------------------------------- data required time 9.97 data arrival time -10.04 ----------------------------------------------------------- slack (VIOLATED) -0.07 最大借用时间调整可以注意到Time Borrowing Information一栏列出了最大借用时间可以看出它取决于开启沿和关闭沿之间的脉宽和锁存器的建立时间如图6所示。图6 因建立时间要求而减少的最大可借用时间为了获取更高精度除此之外还会根据时钟延迟、时钟不确定度和时钟悲观路径移除(CRPR)进一步调整最大借用时间。时钟延迟开启沿和关闭沿的时钟延迟不同会影响它们之间的脉宽自然也会影响最大借用时间如图7所示。图7 考虑延迟后的最大可借用时间调整时钟不确定度开启沿和关闭沿的时钟不确定度不同会影响它们之间的脉宽自然也会影响最大借用时间如图8所示。图8 考虑不确定度后的最大可借用时间调整时钟悲观路径移除时钟悲观路径移除的效果类似于时钟不确定度会使时钟边沿发生偏移但不同之处在于它是使延迟估计更不悲观而时钟不确定度则是使延迟估计更悲观。开启沿和关闭沿的时钟悲观路径移除差异会影响它们之间的脉宽自然也会影响最大借用时间如图9所示。图9 考虑CRPR后的最大可借用时间调整考虑了以上所有因素后的最大可借用时间结果如下所示。Time Borrowing Information --------------------------------------------------- CLK nominal pulse width 5.00 clock latency difference -1.00 clock uncertainty difference 0.30 CRPR difference -0.10 library setup time -0.40 --------------------------------------------------- max time borrow 3.80 ---------------------------------------------------借用的时间和给予的时间正如前文所示借用的时间和给予的时间并不总是相等这是因为在计算借用的时间时尽管时钟延迟、时钟不确定度和时钟悲观路径移除都会导致开启沿偏移同时影响最大借用时间但对于下一条时序路径的分析来说开启沿此时用于发射数据只有时钟延迟会影响发射路径而时钟不确定度和时钟悲观路径移除则只影响捕获路径给予的时间会根据时钟不确定度和时钟悲观路径移除进行调整如图10所示。其中Nominal opening edge指的是只考虑时钟延迟的开启沿。图10 借用的时间和给予的时间下面是时序报告中借用的时间和给予的时间。Time Borrowing Information --------------------------------------------------- CLK nominal pulse width 5.00 clock latency difference -1.00 clock uncertainty difference 0.30 CRPR difference -0.10 library setup time -0.40 --------------------------------------------------- max time borrow 3.80 --------------------------------------------------- actual time borrow 3.40 open edge uncertainty -2.10 open edge CRPR 0.30 --------------------------------------------------- time given to startpoint 1.60 ---------------------------------------------------特殊情况在大多数情况下输入数据在开启沿之前到达不会导致时序借用输入数据在锁存器透明状态时到达则会产生时序借用。当发生时序借用时以锁存器为终点的时序路径中会出现time borrowed from endpoint以锁存器为起点的时序路径中会出现time given to startpoint。然而在某些情况下输入数据恰好在开启沿之前到达但也可能产生时序借用。这发生在锁存器的D2Q延迟大于Clk2Q延迟并且输入数据在开启沿一定范围内由D2Q延迟和Clk2Q延迟的差值决定到达如图11所示。图11 负的借用时间在这种情况下下一条时序路径的数据发射时间是由数据到达时间加上D2Q延迟决定的而不是像一般情况那样由开启沿时间加上Clk2Q延迟决定。由于此时借用的时间为负以锁存器为终点的时序路径中会出现time given to endpoint以锁存器为起点的时序路径中会出现time borrowed from startpoint其绝对值不能超过D2Q延迟和Clk2Q延迟的差值。
